1. Field of the Invention
This invention relates generally to parallel analog-to-digital converters (ADCs) and more particularly to techniques for reducing output errors on a flash ADC.
2. Description of the Related Art
The objective of analog-to-digital (xe2x80x9cADCxe2x80x9d) converters is to receive an analog signal and produce an error free digitized version of that analog signal. A well known ADC circuit is a parallel or xe2x80x9cflashxe2x80x9d ADC, which receives an analog signal to be digitized and compares its voltage to a set of reference voltages. As illustrated in FIG. 1, for xe2x80x9cnxe2x80x9d bits of resolution in the ADC""s digital output, a known voltage is applied to a ladder of 2n series resistors 110 to provide reference voltages at the nodes between the resistors 110. Comparators 120, typically implemented with high gain amplifiers, receive respective reference voltages at one input and the analog input signal at another input to produce either a low output (binary 0) if the comparator""s reference voltage is greater than the analog input, or a high or xe2x80x9cactivexe2x80x9d output (binary 1) if the analog input is higher than the comparator""s reference voltage. Ideally, the resulting digital comparator 120 outputs, referred to as xe2x80x9cthermometer code,xe2x80x9d are a series of binary 0s for comparators which receive reference voltages greater than the analog input signal, and a series of binary is for comparators which receive a reference voltage less than the analog input signal. The transition from binary 0s to 1s indicates the amplitude of the analog input signal.
In a typical flash-type Analog-to-Digital Converter (ADC) shown in FIG. 1, the task of the digital back-end is to process the thermometer code output of the 2nxe2x88x921 comparators 120 and generate an equivalent n-bit digital binary output. There are numerous ways of achieving this goal. One commonly used scheme is to configure a 1-of-(2nxe2x88x921) decoder 130 followed by a Read-Only-Memory (ROM) 140 look-up table. The decoder 130 detects the 0-to-1 transition in the thermometer code output of the comparators 120 and activates the corresponding output line which enables a ROM address to place its contents on the output data-bus.
When high slew-rate input signals are sampled, timing skew between the clock and signal paths and differences in comparator 120 response-times can cause the effective strobe point of the comparators to be different. This can lead to an irregular thermometer code pattern where a 0 can be found below a 1 or a 1 above a 0. These unwanted irregularities are known as xe2x80x9cbubblesxe2x80x9d and if they are not adequately suppressed they can cause severe ROM output errors, known as xe2x80x9csparklexe2x80x9d code errors, as more than one address can become enabled at the same time. These large output errors can have significant impact on the Signal-to-Noise Ratio (SNR) performance of the ADC.
Several methods of preventing bubbles from causing sparkle code errors have been reported. The suppression scheme may be implemented in the 1-of-(2nxe2x88x921) decoder and/or in the ROM. Some of the well known schemes include xe2x80x9cDemocratic Decodingxe2x80x9d (C. W. Mangelsdorf, xe2x80x9cA 400 MHz Input Flash Converter with Error Correctionxe2x80x9d, IEEE J. Solid-State Circuits, vol. 25, pp. 184-191, February 1990); xe2x80x9cQuasi-Grayxe2x80x9d Code (Y. Akazawa et al., xe2x80x9cA 400MSPS 8-bit Flash A/D Conversion LSIxe2x80x9d, in ISSCC Dig. Tech. Papers, pp. 98-99, February 1987); xe2x80x9cHalf-Grayxe2x80x9d Code (U.S. Pat. No. 5,633,636. Title: Half-Gray Digital Encoding Method and Circuitryxe2x80x9d. Date: May 27, 1997); xe2x80x9cBit-Swapxe2x80x9d techniques (V. E. Garuts et al., xe2x80x9cA Dual 4-bit 2Gs/s Full Nyquist Analog-to-Digital Converter using a 70 ps Silicon Bipolar Technology with Borosenic-Poly Process and Coupling-Base Implantxe2x80x9d, IEEE J. Solid-State Circuits, vol. 24, pp. 216-222, April 1989); and several multi-level ROM topologies. Most of these schemes, however, are quite complex and more suitable to lower sampling rates or, alternatively, require a high-speed bipolar technology which will dissipate large amounts of power.
A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.